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Emerging Technologies 2018 Session Listing

The program is subject to change in the weeks leading up to the conference. Check back here for the latest schedule, or follow us on Twitter External link symbol for real-time notice of updates to the program.

Session A1: Devices, Circuits and Systems

Start Time: 13:30, Wednesday, May 09
Room: Mt. Currie North
Chaired by Mohammad Darwish, Aplicata Technologies ( and Yushi Zhou, Lakehead University (

  • 13:30 Tetsuo Endoh, Tohoku University (

    Impact of nonvolatile brain-inspired VLSIs with CMOS/MTJ hybrid technology

    Conventional CMOS type VLSIs face the insurmountable problems on intelligent applications such as image recognition, automotive car control, video surveillance, and so forth.


    In this invited talk, it is discussed that CMOS/MTJ hybrid VLSI technology has an impact in brain inspired computing and neuromorphic computing. We have developed a novel associative processor employing nonvolatile memories base on our IPMA type perpendicular-MTJ and fabricated it under 90nm-CMOS/70nm-p-MTJ hybrid process on 300mm-wafer. An intelligent power-gating technique leveraging the non- volatility, high access speed and unlimited endurance features of p-MTJs is employed to shut down idle circuit blocks during not only standby periods but also full operation periods for autonomously activating currently-accessed memory cells. The measured average operation power of the prototype chip is only 600μW (Conventional CMOS type associative processor’s power is over 100W).


    Acknowledgment: This work is supported by CIES’s Industrial Affiliation on STT-MRAM program, ACCEL under JST, OPERA under JST.


    [1] T. Endoh and Y.Ma, MMM2016 (Invited) [2] T.Endoh, The 9th MRAM Global Innovation Forum 2017 (Invited)

  • 13:50 Carlos Galup Montoro, Universidade Federal de Santa Catarina (

    Ultra low voltage/power LNA and mixers

  • 14:10 Naoya Onizawa, Tohoku University (

    Energy-efficient brainware LSI based on stochastic computation

    Stochastic computation has been recently studied for soft-error-resilient hardware and approximate computing, such as image processing, machine learning, and deep neural networks. This talk reviews stochastic computation and discusses the advantages and disadvantages with the recent developments in haredware. In addition, stochastic- computation based brainware LSIs (BLSIs) for vision information processing are introduced and discussed in terms of energy efficiency.

  • 14:30 Arash Sheikholeslam, University of British Columbia (

    Proton transport and its effects on transistor aging

    Hydrogen is used to passivate silicon dangling bonds at the dielectric/channel interface of metal—oxide—semiconductor field-effect transistors (MOSFETs). The untreated dangling bonds can shift the threshold voltage and as a result decrease the transistor’s switching speed. One reliability issue with such transistors is that the passivating hydrogens dissociate from the Si-H bond and diffuse as a proton complex inside the gate dielectric (SiO2). Molecular dynamics with reactive force fields is shown to be an accurate method in understanding and predicting proton diffusion kinetics at the dielectric/channel interface as well as the bulk dielectric material. The model is first validated against experimental data and then used for making predictions wherever experimental data is not available.

  • 14:50 Hassan Maher, Université de Sherbrooke (

    Normally-off GaN HEMT transistor for high power applications

    In today’s fast evolution and expansion of wireless communications, the GaN HEMT is a good candidate taking advantage of its high frequency performance, high breakdown voltage and material robustness. For the next generations of RF power amplifiers, GaN-based technology is the most promising to satisfy the more and more demanding specifications of the market. The standard GaN-HEMT is a depletion mode device (D-mode), which is normally-on. RF circuit designers claim for normally-off devices (E- mode) to reduce circuit complexity and power consumption. On other hand, the normally-off aspect is mandatory for the High power application due to the safety issues. In this presentation we will illustrate the different available technics to fabricate a normally-off GaN- HEMT and the strength and the draw-back of each technic.

  • 15:10 Sarit Dhar, Auburn University (

    Silicon carbide MOSFET science and technology

    Metal-Oxide-Semiconductor field-effect transistors (MOSFETs) fabricated using 4H-SiC are an enabling technology for various high voltage (>900 V) power convertors and invertors, important in automotive and renewable energy applications. While commercial 4H-SiC MOSFETs offer significantly lower conduction losses compared to conventional Silicon for blocking voltages ≥900 V, the low channel electron mobility (~20 cm2 V-1 s-1) is a critical limitation for competitive penetration into lower voltage (`600 V) discrete electronic markets. In addition, reliable high temperature (>200°C) operation is also a key factor for various, especially for automobile and aircraft applications. At the heart of both these issues lie electronic defects or traps at the oxide (SiO2)/semiconductor (4H-SiC) interfaces and in the near interfacial SiO2. Low inversion channel electron mobility has been a traditional challenge due to a high density of near interfacial electron traps (NIT), energetically located near the conduction band of 4H-SiC and spatially located at or near the gate oxide- 4H-SiC interface. In addition to mobility degradation, such traps can negatively impact device stability under bias temperature stress conditions [1]. Introducing about a monolayer (1015 cm-2) of nitrogen atoms at the SiO2/SiC interface [2] reduces the trap densities which improves the channel mobility as well as gate oxide reliability, making commercial 4H-SiC MOSFETs a reality.


    In this talk the current status of 4H-SiC MOSFETs will be reviewed highlighting the importance of dielectric/SiC interface optimization. Results demonstrating lower NIT density and higher channel mobility than the state-of-the —art (~120 cm2 V-1 s-1 at room temperature on lightly doped p-SiC) using dielectrics formed by doping of SiO2 with Phosphorus [3,4] and Boron [5] will be presented. In addition, the effect of a very thin (~10 nm) n-type doped layer on p-type SiC surface, formed by the implantation of Sb [6] will also be discussed. The mobility limiting mechanisms in these novel MIS structures will be discussed. The physical nature of interface charges in SiO2 based planar and trench devices analyzed by electrical/ physical measurements and validated by atomistic calculations will be described.


    Acknowledgements: Results to be presented in this talk have been obtained by financial support from the U.S. Army Research Laboratory, the U.S. National Science Foundation, II-VI Foundation Block-Gift Program, DOE NCSU Power America Center and Texas Instruments Inc.


    [1] A. J. Lelis et al., IEEE Trans. Electron Devices, 55, 1835 (2008). [2] G. Liu et al., Appl. Phys. Rev., 2, 021307 (2015). [3] D. Okamoto et al., Appl. Phys. Lett., 96, 203508 (2010). [4] C. Jiao et al., J. Appl. Phys., 119, 155705 (2016). [5] D. Okamoto et al., IEEE Electron Device Lett., 35, 1176 (2014). [6] A. Modic et al., IEEE Electron Device Lett., 38, 1433 (2017).

  • 15:30 COFFEE BREAK (Mt. Curie Foyer, Sutcliffe Foyer)


  • 15:50 Jia Di, University of Arkansas (

    Advantages and applications of asynchronous circuits

    Asynchronous circuits do not have clock. Handshaking protocols are used instead to control the circuit operation. Born with a series of advantages, e.g., flexible timing requirement, high energy efficiency, average-case performance, high modularity, and low EMI, asynchronous circuits have not been developing nearly as fast as synchronous counterparts. This is due to the drawbacks of asynchronous circuits (e.g., larger area, slower speed) and the lack of industry-standard EDA tool support. However, for a variety of applications, asynchronous circuits have unique advantages. This talk will introduce the basic concept and advantages of asynchronous circuits and discuss several of such applications suitable for asynchronous circuits with design examples and results.

  • 16:10 Fei Yuan, Ryerson University (

    All-digital time-mode approaches for mixed analog-digital signal processing

    CMOS technology scaling has always been geared towards optimizing the performance of digital circuits at the expense of the deteriorating performance of analog circuits with shrinking voltage headroom, worsening device mismatch, and deteriorating linearity the most critical. Scaling-rooted performance deterioration of analog circuits can be compensated using digital means to some degree, however, at the cost of increased silicon area and power consumption. Technology scaling, on the other hand, has greatly improved the switching time of digital circuits. Time-mode signal processing where information is represented by time difference between the occurrence of digital events e.g. the rising or falling edges of digital signals offer a viable and technology friendly means to combat stiff difficulties encountered in mixed analog-digital systems. Time-mode circuits are digital systems capable of performing analog and mixed analog-digital signal processing without using power-greedy and speed-impaired digital signal processors, and therefore possess the inherent characteristics of digital circuits such as technology compatibility, programmability, portability, better immunity to disturbances, and rapid design turnaround time that are not possessed by their analog counterparts. Time-mode approaches have found a broad spectrum of emerging applications in mixed analog-digital systems including vehicle navigation systems, analog-to-digital data converters, finite and infinite impulse response filters, all digital phase-locked loops and frequency synthesizers, and high-speed data links, to name a few. This talk reports the latest research findings in this exciting emerging field with a focus on all-digital time-mode delta-sigma data converters.

  • 16:30 Seung-Tak Ryu, KAIST ( with J-H. Jang

    Study on various ADC architectures with SAR ADCs

  • 16:50 Amir Masnadi, University of British Columbia (

    Sub-THz to THz signal generators on CMOS: Techniques for improving DC-to-RF efficiency

    Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This presentation shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. In this talk after showing existing bottlenecks of (sub)THz generation on CMOS, some techniques will be presented to simultaneously generate high output power while achieving superior DC-to-RF efficiency.

  • 17:10 Ramesh Harjani, University of Minnesota ( with S. Chaubey

    Ultra low voltage LDO regulator design

    We present the first fully integrated analog low dropout regulator (LDO) for sub-0.5V supply voltages. The LDO can operate from 0.3V-to-1.0V input voltage, and can sustain a load variation of 10mA-to-100mA at 1.0V input and 5mA-to-25mA at 0.3V input. It achieves a peak 99.1% current efficiency for a 100mA load at 0.9V output voltage. We introduce a negative charge pump based adaptive offset for the pass FET which provides gate-source headroom at input operation voltages normally reserved for digital LDOs. The 32 phase charge pump runs at a frequency of 3GHz with a ripple of ~3mV. The prototype was fabricated in TSMC’s 65nm GP CMOS.

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