Emerging Technologies 2018 Session Listing
The program is subject to change in the weeks leading up to the conference. Check back here for the latest schedule, or follow us on Twitter for real-time notice of updates to the program.
Session A2: Memories and Computing
Start Time: 09:00, Thursday, May 10
Room: Mt. Currie North
Chaired by Mohammad Darwish, Aplicata Technologies (email@example.com)
- 9:00 Kerem Camsari, Purdue University
Stochastic p-bits for invertible logic
Digital electronics is based on deterministic bits that are either a "0" or "1". In this talk, I will outline our recent work on "Probabilistic Spin Logic (PSL)", that is based on probabilistic bits (p-bits) that fluctuate randomly between "0" and "1" in a controllable manner. We have shown that "p-circuits" built out of p-bits can be a viable hardware framework for a wide range of applications including Bayesian Networks, problems of Optimization and a new kind of Boolean logic that is "invertible". Not only does a Boolean p-circuit provide outputs specified by inputs, but also all inputs consistent with a given output. I will illustrate how this remarkable property can be exploited with different examples. I will describe how the basic equations of PSL can be naturally mapped to the physics of existing spintronic devices, such as the commercially developed embedded MRAM, but I will also talk about non-magnetic representations of p-bits and p- circuits.
- 9:20 Tosiron Adegbija, University of Arizona
Potentials of microarchitecture adaptability for performance, energy, and security optimizations
Emerging embedded systems execute memory- and compute-intensive applications with vast data streams and dynamic execution characteristics. In order to achieve optimization goals (e.g., performance, energy, and security), system resources must be dynamically adapted to support dynamic data complexity and execution variability. This talk will explore some of the benefits of, and techniques for, enabling adaptability as an inherent feature of emerging microarchitectures, in order to improve energy efficiency, performance, and security. We will first discuss recent work on leveraging configurability as a low-overhead defense against cache side channel attacks. We will then discuss new techniques for improving the energy efficiency of emerging non-volatile memory-based caches through logical retention time adaptability.
- 9:40 Ajay Joshi, Boston University
Electro-photonic NoC designs for kilocore systems
The increasing core count in manycore systems requires a corresponding large Network-on-chip (NoC) bandwidth to support the overlying applications. However, it is not possible to provide this large bandwidth in an energy-efficient manner using electrical link technology. To overcome this issue, photonic link technology has been proposed as a replacement. In this talk, I will discuss the limits and opportunities for using electrical and photonic links to design the NoC architectures for a future Kilocore systems. We explored three different NoC designs: ElecNoC, an electrical concentrated two-dimensional- (2D) mesh NoC; HybNoC, an electrical concentrated 2D mesh with a photonic multi-crossbar NoC; and PhotoNoC, a photonic multi-bus NoC. We considered both private and shared cache architectures, and to leverage the large bandwidth density of photonic links we investigated the use of prefetching and aggressive non-blocking caches. Our analysis using contemporary Big Data workloads shows that the non-blocking caches with a shared last-level cache can best leverage the large bandwidth of the photonic links in the Kilocore system. Compared to ElecNoC-based and HybNoC-based Kilocore systems, a PhotoNoC-based Kilocore system achieves up to 2.5x and 1.5x better performance, respectively, and can support up to 2.1x and 1.1x higher bandwidth, respectively, while dissipating comparable power in the overall system.
- 10:00 Massimiliano Di Ventra, University of California, San Diego
Memcomputing: a brain-inspired efficient computing paradigm
Which features make the brain such a powerful and energy-efficient computing machine? Can we reproduce them in the solid state, and if so, what type of computing paradigm would we obtain? I will show that a machine that processes information directly in memory, like our brain, and is endowed with intrinsic parallelism and information overhead - namely takes advantage, via its collective state, of the network topology related to the problem - has a computational power far beyond our standard digital computers. We have named this novel computing paradigm "memcomputing". As examples, I will show the polynomial-time solution of prime factorization, the search version of the subset-sum problem, and approximations to the Max-SAT beyond the inapproximability limit using polynomial resources and self-organizing logic gates, namely gates that self-organize to satisfy their logical proposition. I will also demonstrate that these machines are described by a topological field theory, and they compute via an instantonic phase, implying that they are robust against noise and disorder. The digital memcomputing machines that we propose can be efficiently simulated, are scalable and can be easily realized with available nanotechnology components.
- 10:20 COFFEE BREAK
(Mt. Curie Foyer, Sutcliffe Foyer)
- 10:40 Bastien Giraud, CEA
Smart memory solutions for emerging technologies
This talk presents our recent research activities about memory design solutions to address new emerging markets.
We have studied advanced memory solutions on different technologies such as monolithic 3D CoolCubeTM, Tunnel-FET (TFET) and Resistive RAM. Firstly, the presented 4T SRAM bitcell in 3D CoolCube shows 30% area reduction with respect to a standard planar 6T bitcell and a strengthened stability thanks to data dependent dynamic back bias. Secondly, a reconfigurable CAM/SRAM circuit outperforms the state of the art, with operations at 1.56GHz and 0.13fJ/bit energy per search. Furthermore, the proposed TFET-based designs are competitive in terms of area and performance, while reducing significantly the leakage currents. Thirdly, the proposed compensation techniques for crosspoint memory architecture enable large memory arrays, while reducing the impact of temporal and spatial variations. Finally, our software platform to implement the proposed in-memory computing concept will be exposed.
For the sake of clarity, the talk will focus on a subset of these activities.
- 11:00 Alessandro Paccagnella, Università degli Studi di Padova
Non-volatile memories for space applications: from planar to 3D devices
This talk will introduce ionizing radiation effects affecting non-volatile floating gate memories, with a specific focus on the space environment. We will explore in particular the single event effects - SEE, and how they are changing with the continuous technological scaling of the minimum feature size. As a guideline for such exploration, we will follow the single event effects occurring in the NAND Flash cell arrays. We will also present some recent results obtained in 3D components, where a sophisticated vertical integration process gives rise to unexpected SEE results and may shine new light on the interpretation of SEE phenomena observed in planar components. In fact, the cell circular shape and the fact that the tunnel oxide and interpoly dielectric blocking layers are perpendicular to the semiconductor substrate, make it possible to gain insight into the underlying upset mechanism.
- 11:20 Zhengya Zhang, University of Michigan
Spiking neural net accelerators for embedded computer vision applications
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