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Emerging Technologies 2018 Session Listing

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Session A4: Circuits and Systems Design and Manufacture

Start Time: 09:00, Friday, May 11
Room: Sutcliffe A
Chaired by Peter Wilson, Alpha & Omega Semiconductor (peterhwilson@msn.com)

  • 9:00 Gord Harling, CMC Microsystems (gharling@innotime.ca)

    TBA

  • 9:20 Laleh Behjat, University of Calgary (laleh@ucalgary.ca)

    From extremely large to super small scale: how optimization is used in the electronic design automation

    The Integrated Circuits (IC) industry has been able to double the number of the transistors, the switching elements, in a computer chip every 18 months. This is done by reducing the size of the transistors. Currently, transistor sizes range between14 to 7 nm. This growth in technology has on one hand forced the engineers to solve very large scale problems, while on the other hand, they have to deal with unavoidable uncertainties that exist because of the small sizes of the transistors. In this talk, we will discuss case studies in IC physical design where large scale problems or problems that include uncertainties are solved using convex optimization methods, and how convex optimization methods can be integrated with heuristics to find reasonably good solutions in low runtime.

  • 9:40 Takashi Matsukawa, National Institute of Advanced Industrial Science and Technology (t-matsu@aist.go.jp)

    Process challenges for further scaling of FinFETs

    Further scaling of FinFETs as an advanced CMOS platform needs reduction of the fin thickness and suppression of the characteristics variability. A dominant origin of the characteristics variability for the FinFETs with an undoped channel is work function variation (WFV) of the gate electrode due to granularity of the gate material. An effective technology to suppress the WFV is utilization of amorphous metals. The FinFETs with the amorphous metal gate exhibit significant suppression of the variability. The use of the amorphous metal gate can also suppress the flicker noise which has been a critical obstacle to reduction of the analog component size in SoCs. The fin thickness reduction to suppress the short channel effect causes difficulty in doping the fin by ion implantation. Consequently, the residual damage due to the ion implantation causes significant increase in the parasitic S/D resistance, its fluctuation and anomalous off-leakage known as gate induced drain leakage. Our experimental study reveals that the use of lighter ion species, i.e., P instead of As, can lighten the impacts of the residual damage. Furthermore, we have implemented damageless doping by the use of spin-coated phosphorus doped silica.

  • 10:00 Gene A. Frantz, Octavo Systems LLC (gene.frantz@octavosystems.com) with M. Murtuza

    The next frontier of integration: the system in a package

    We have enjoyed the technical advancements of integrated circuits for a half of a century. It began with a simple concept of putting more than one device on a substrate. Our drive has been to increase performance while reducing cost and power dissipation. The goal was a System on a Chip (SoC). But there is a complication. As we took on the task of driving the three vectors of performance (clock, cost and power) the manufacturing processes began to diverge. What started as a drive to the SoC found the drive diverging into four different directions and we found ourselves with SubSystems on a Chip rather than a complete System on a Chip. This paper will take a look at the underlying issues we are facing and then discussing what might be a good solution to the drive towards system integration.

  • 10:20 COFFEE BREAK (Mt. Curie Foyer)

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  • 10:40 Maciej Ogorzalek, Uniwersytet Jagiellonski Krakow (maciej.ogorzalek@uj.edu.pl) with K. Grzesiak-Kopec

    Behavior-oriented 3D IC layout design

    Collective behavior and self-organization are common phenomena in biological systems that have been successfully applied to many different domains, including economics, social science, game programming or mobile robotics. They are often modeled and analyzed by means of physical systems, where individuals are treated as particles that interact locally and collective behavior emerges without any global control. We have proposed an agent-based flocking model to solve the 3D chip volume minimization. Design goals and constraints were defined by the means of steering behaviors, namely cohesion, separation and alignment. Now, we investigate the influence of neighbor preferences on the spatial sorting of chip module agents in terms of shape and packing. Different individual movement strategies are presented that are strongly correlated to the agent spatial position in a group. In such a way, various IC layout design requirements may be fulfilled, such as the total wire-length minimization or the hot-spot problem reduction. The approach is illustrated by the example application implemented using Godot that is an advanced open source game engine.

  • 11:00 Sidney Tsai, IBM (htsai@us.ibm.com)

    Neuromorphic hardware acceleration of neural network training using analog memory

    Deep neural networks (DNNs) are a family of neuromorphic computing architectures that have recently made significant advances in difficult machine learning problems such as image/object recognition, speech recognition, and machine language translation. Analog non-volatile memories (NVM) can efficiently accelerate inference and training with back-propagation of DNNs by performing parallelized multiply-accumulate operations in the analog domain, at the location of weight data, using underlying physics. In this talk, I will briefly review our previous work towards achieving competitive performance (classification accuracies) for such DNNs with Phase-Change Memory (PCM) and show ways to improve accuracy further by improving dynamic range and excessive weight-update asymmetry of the memory element. Circuit approximations that improve network parallelism without significantly degrading classification accuracy and Power/speed advantages of such approach over conventional Von-Neumann processors, e.g. today’s CPU and GPUs, will also be discussed.

  • 11:20 Jacques C. Rudell, University of Washington (jcrudell@u.washington.edu)

    Integrated CMOS transceivers design towards flexible full duplex (FD) and half duplex (HD) wireless systems

    This paper surveys the challenges and the current state-of-the-art in the areas of full duplex (FD) and frequency division duplex (FDD) integrated transceivers. Implementation hurdles in the form of the linearity, noise, bandwidth (BW) and power consumption of transmitter (TX) self-interference (SI) cancellation circuitry are explored. The difficulty of performing SI cancellation is heavily influenced by the modulation method, the maximum TX power output and the receiver (RX) channel BW. These issues are discussed using several recent publications as implementation examples of single-chip FD radios that range in performance from low-power cancellation techniques, to transceivers which target broad channel bandwidths using high-output-power Power Amplifiers, thus requiring deep SI cancellation. While an attempt is made to highlight works across the community, a more in-depth look at several 40-nm CMOS devices which range in performance from a narrowband Bluetooth low-energy (BLE) transceiver to analog-front-ends which integrate a +24dBm power amplifier (PA) with a dual-point feedforward cancellation architecture for broadband (>40MHz) and deep SI suppression (>50dB) are discussed.

  • 11:40 Shamik Das, Mitre Corporation (sdas@mitre.org)

    Performance assessment of gapless graphene logic circuit designs

    We present models, designs, and simulation results for logic circuits based upon graphene ballistic deflection transistors (GBDTs). The use of graphene in conventional semiconductor circuits has proved difficult due to its negligible bandgap. GBDTs might avoid this deficiency by electrostatically steering currents through a two-dimensional charge transport medium. Simulation results are presented for a GBDT-based inverter and full adder that are projected to operate twice as fast as conventional CMOS circuits, at the cost of much lower transistor density. The GBDT-based circuits presented in this paper would be well suited for high-speed, high-duty-cycle applications, including high-throughput networking and high-performance computing.

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