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Emerging Technologies 2018 Session Listing

The program is subject to change in the weeks leading up to the conference. Check back here for the latest schedule, or follow us on Twitter External link symbol for real-time notice of updates to the program.

We plan to have a firm program available no later than February 5, 2018.

Session A4: Circuits and Systems Design and Manufacture

Start Time: 09:00, Friday, May 11
Room: TBD
Chaired by Chair to be Announced

  • Laleh Behjat, University of Calgary (laleh@ucalgary.ca)

    From extremely large to super small scale: how optimization is used in the electronic design automation

    The Integrated Circuits (IC) industry has been able to double the number of the transistors, the switching elements, in a computer chip every 18 months. This is done by reducing the size of the transistors. Currently, transistor sizes range between14 to 7 nm. This growth in technology has on one hand forced the engineers to solve very large scale problems, while on the other hand, they have to deal with unavoidable uncertainties that exist because of the small sizes of the transistors. In this talk, we will discuss case studies in IC physical design where large scale problems or problems that include uncertainties are solved using convex optimization methods, and how convex optimization methods can be integrated with heuristics to find reasonably good solutions in low runtime.

  • Gene A. Frantz, Octavo Systems LLC (gene.frantz@octavosystems.com) with M. Murtuza

    The next frontier of integration:  the system in a package

    We have enjoyed the technical advancements of integrated circuits for a half of a century. It began with a simple concept of putting more than one device on a substrate. Our drive has been to increase performance while reducing cost and power dissipation. The goal was a System on a Chip (SoC). But there is a complication. As we took on the task of driving the three vectors of performance (clock, cost and power) the manufacturing processes began to diverge. What started as a drive to the SoC found the drive diverging into four different directions and we found ourselves with SubSystems on a Chip rather than a complete System on a Chip. This paper will take a look at the underlying issues we are facing and then discussing what might be a good solution to the drive towards system integration.

  • Alex James, Nazarbayev University (apj@ieee.org)

    Large-scale simulation of memristive neural systems

    In the last decade, memristor has found its use in sensory processing systems for neuromorphic applications, cognitive algorithms, intelligent memory arrays and hierarchical temporal memories. The small size, ease of programmability, low leakage currents, ability to maintain resistance states and CMOS compatibility make the memristor a useful device for neurochip implementations. The possibility of using memristors to mimic neural circuits as well as to implement learning memory for various Spatio-temporal pattern recognition and neuromorphic computing applications makes it further a versatile device. However, in this early stages of development and exploration, the practical realisation of computational intelligence applications requires the development of in-depth theory, modelling, simulation and implementation of the memristors in large scale arrays and networks. The area of the large-scale network is explored and the advancement in this emerging field summarised for different computational intelligence applications such as artificial life, artificial cellular networks, bio-inspired networks, and intelligence over the internet of things.

  • Tanbir Haque, InterDigital (tanbir.haque@interdigital.com)

    Developing flexible architectures for wideband data reception and rapid interference detection for cognitive radio type applications

  • COFFEE BREAK (FOYER)

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  • Salvador Pinillos Gimenez, Centro Universitário da FEI (sgimenez@fei.edu.br)

    Layout techniques for MOSFETs

  • Maciej Ogorzalek, Uniwersytet Jagiellonski Krakow (maciej.ogorzalek@uj.edu.pl) with K. Grzesiak-Kopec and P. Oramus

    Behavior-oriented 3D IC layout design

  • Fei Yuan, Ryerson University (fyuan@ryerson.ca)

    All-digital time-mode approaches for mixed analog-digital signal processing

  • Amalio Fernandez-Pacheco, University of Cambridge (af457@cam.ac.uk)

    3D nano-printing of magnetic circuits

  • Takashi Matsukawa, National Institute of Advanced Industrial Science and Technology (t-matsu@aist.go.jp)

    Process challenges for further scaling of FinFETs

  • Jayna Sheats, Terecircuits (sheats@terecircuits.com)

    Process technology for heterogeneous integration

  • Yue Fu, Crosslight Software (fred@crosslight.com)

  • Carlos Gracios-Marin, CERN-European Organization for Nuclear Research (cgracios@cern.ch)

  • Hanju Oh, University of Pennsylvania (hanjuoh@seas.upenn.edu)

  • Jacques C. Rudell, University of Washington (jcrudell@u.washington.edu)

  • Sidney Tsai, IBM (htsai@us.ibm.com)

    Neuromorphic hardware acceleration of neural network training using analog memory

    Deep neural networks (DNNs) are a family of neuromorphic computing architectures that have recently made significant advances in difficult machine learning problems such as image/object recognition, speech recognition, and machine language translation. Analog non-volatile memories (NVM) can efficiently accelerate inference and training with back-propagation of DNNs by performing parallelized multiply-accumulate operations in the analog domain, at the location of weight data, using underlying physics. In this talk, I will briefly review our previous work towards achieving competitive performance (classification accuracies) for such DNNs with Phase-Change Memory (PCM) and show ways to improve accuracy further by improving dynamic range and excessive weight-update asymmetry of the memory element. Circuit approximations that improve network parallelism without significantly degrading classification accuracy and Power/speed advantages of such approach over conventional Von-Neumann processors, e.g. today’s CPU and GPUs, will also be discussed.

  • Peter Wilson, Transphorm (peterhwilson@msn.com)

 

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