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Emerging Technologies 2018 Session Listing

The program is subject to change in the weeks leading up to the conference. Check back here for the latest schedule, or follow us on Twitter External link symbol for real-time notice of updates to the program.

We plan to have a firm program available no later than February 5, 2018.

Session B1: Nanoscale Devices and Circuits

Start Time: 13:30, Wednesday, May 09
Room: TBD
Chaired by Chair to be Announced

  • Krishna Saraswat, Stanford University (saraswat@stanford.edu)

    Emerging interconnect technologies for nanoelectronics

  • Maxime Hugues, CNRS-CRHEA (mh@crhea.cnrs.fr)

    The development of AlGaN/GaN and ZnMgO/ZnO heterostructures for THz devices

  • Hagen Klauk, Max Planck Institute for Solid State Research (h.klauk@fkf.mpg.de)

    Submicron-channel-length organic thin-film transistors

    Organic thin-film transistors (TFTs) can typically be fabricated at temperatures below 150 °C and thus not only on glass, but also on unconventional substrates, such as plastics and paper. This makes organic TFTs potentially useful for flexible, large-area electronics applications, such as rollable or foldable displays and conformable sensor arrays. In some of the more advanced applications envisioned for organic TFTs, the TFTs have to control electrical signals of a few volts at frequencies of several megahertz. The first requirement for achieving high switching frequencies is efficient charge transport in the semiconductor, which can be met by choosing organic semiconductors that provide good molecular ordering and large carrier mobilities. The second and more critical requirement is a small channel length. To meet this requirement, we have developed a process in which the TFTs are patterned using high-resolution silicon stencil masks. With this process, bottom-gate, top-contact organic TFTs with a channel length as small as 300 nm can be fabricated. For 11- stage complementary and unipolar ring oscillators based on TFTs with a channel length of 1 μm, signal propagation delays per stage as short as 6.6 μs and 420 ns have been measured at a supply voltage of 3 V.

  • Ji Ung Lee, SUNY Polytechnic Institute (jlee1@sunypoly.edu)

    Reconfigurable logic devices in 2D materials

  • Andreas Ruediger, INRS (ruediger@emt.inrs.ca)

    CMOS compatible ferroelectric tunnel junctions

  • Christopher Künneth, Munich University of Applied Sciences (christopher.kuenneth@googlemail.com)

    Explaining the ferroelectricity and pyroelectricity in HfO2 and ZrO2 thin films from an interface driven size effect with DFT

  • COFFEE BREAK (FOYER)

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  • Felix Holzner, SwissLitho (holzner@swisslitho.com)

    NanoFrazor lithography: single nanometer device fabrication without charged particles

  • Fabrice Vallee, Université de Lyon (fabrice.vallee@univ-lyon1.fr)

    Control of mechanical energy damping at the nanoscale

  • Jan Dubowski, Université de Sherbrooke (Jan.J.Dubowski@USherbrooke.ca)

  • Peng Zhou, Fudan University (pengzhou@fudan.edu.cn)

 

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