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Emerging Technologies 2018 Session Listing

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Session B2: Next-Generation Wireless

Start Time: 09:00, Thursday, May 10
Room: Sutcliffe B
Chaired by Peter Wilson, Alpha & Omega Semiconductor (

  • 9:00 Eran Socher, Tel-Aviv University (

    THz CMOS radiating transceivers and arrays for future connectivity and sensing

    The scaling of CMOS circuits has enabled devices with cut-off frequencies around 300GHz and implementation of transmitters and receivers at mm-wave frequencies approaching the THz. This frequency range offers opportunity for both >20Gbps communication links and biomedical applications. However, to make applicative systems at these frequencies, CMOS circuits need to be effectively interfaced to the macro world with low loss and wide bandwidth. In order to take advantage of the short wavelengths, scalable and power efficient designs are needed. In this talk we discuss design innovations for THz transceivers with on-chip antennas. With techniques of suppressing surface modes and harmonic rejection we have demonstrated CMOS radiating transmitters (single elements and arrays) and receivers in the wide range of 24 to 600GHz with efficiencies up to 50% without using a lens or superstrate. Scalable design approaches yield radiated powers of more than 5dBm with power efficiency of more than 5%.

  • 9:20 Farhana Sheikh, Intel (

    Adaptive and multi-mode baseband systems for next generation wireless communication

    System adaptivity has been studied since the mid-60s and recently there has been a surge in interest in self-adaptive systems, especially in the software engineering community, with its main application to cybernetics. In this work, we apply self-adaptivity to multi-mode baseband processing systems for 5G wireless communications to exploit channel characteristics to modify the computation of digital baseband processing subsystems for energy savings. The gains from self-adaptivity are exemplified in the design of lattice reduction aided MIMO detection and extended out to other baseband subsystems such as multi-mode FIR filters, and multi-point FFT computation.

  • 9:40 Suraj Prakash, Texas A&M University (

    Energy-efficient envelope tracking in RF power amplifier for demanding wireless standard

    In our day-to-day life, low battery run-time of portable devices is an instrumental issue with huge growth in functional density. Due to the significant consumption of battery power, a power amplifier is always a bottleneck in enhancing battery run-time. In order to reduce power consumption of a power amplifier, several techniques are used in present portable devices. In these techniques, envelope tracking technique is a ubiquitous approach. An envelope tracking solution needs to be faster enough to accommodate fast- moving envelope signal; at the same time, it needs to be power efficient. However, due to a continuous movement to demanding wideband wireless standards with a high peak-to-average ratio, these aspects are becoming challenging. In this talk, we will see the challenges for an envelope tracking solution due to demanding wireless standards and way to overcome these challenges. Furthermore, we will also see an approach of envelope tracking that helps the technique to be faster and power efficient at the same time.

  • 10:00 Joy Laskar, Maja Systems ( with R. Pelard and J. Sevic

    mmW CMOS products for terabit connectivity

    Since the first demonstration of mmW wireless connectivity in 1895, there has been much interest and promise in the future of mmW gigabit wireless technology. It has been only recently, with the emergence of CMOS based technology and its capacity for low-cost monolithic single-chip integration that one can envision a new class of systems and applications for low delay and high throughput connectivity, which forms the foundation for the 5G revolution. In this presentation, we focus on recent breakthroughs at Maja Systems enabling Terabit wireless connectivity. These products are enabled with highly integrated CMOS radios combined with novel surface mount antenna.

  • 10:20 COFFEE BREAK (Mt. Curie Foyer)


  • 10:40 Yahya Tousi, University of Minnesota (

    Integrated phased arrays for next-generation mm-wave and sub-mm-wave wireless systems

    Millimeter and sub-millimeter wireless systems bring the promise of a new generation of applications capable of wide bandwidth, low latency, and line-of-sight spatial multiplexing. Phased array transceiver architectures that can support a large number of elements while providing accurate phase and amplitude control are fundamental to the realization of such systems. In this talk, we discuss current limitations in scaling the size of a millimeter-wave phased array as well as challenges in accurate control of the beam. Next, we present a distributed approach in designing phased arrays and phase shifters that allow significant improvement in the size of the array as well as the conceivable accuracy of the beam pattern, demonstrating phased array prototypes with better scalability and accuracy than the state-of-the-art.

  • 11:00 Morris Repeta, Huawei (

    5G mm-wave ultra-large-scale-array integration technology

    This paper reports an E-band ultra-large-scale phased array radio for 5G communications. The antenna was implemented in LTCC technology. In order to reduce system/circuit complexity, 8-element sub-arrays are used. These sub-arrays are randomly tiled to disrupt the periodicity in the array in order to keep side lobe level (SLL) and grating lobe level (GLL) low. Limited field of view (LFOV) of ±15o in both Azimuth and Elevation planes is achieved with < -10dBc SLL and 60% efficiency. A boresight and a +15o θo, ϕo beam steered 256-element E-band phased arrays were prototyped with LTCC technology to validate the concept, and a 1024-element design was completed. Measured results are presented and compared with simulations. This design is also scalable if higher antenna gain is required making this proposed phased array a good candidate for next generation high speed 5G communications.


    Implemented in 55nm SiGe BiCMOS, two ASICs were designed to be mounted into the LTCC substrate; 1) the Active Antenna which includes 8 TRX and 2) Up/Down Conversion ASIC that will the feed TX and RX signals to an array of Active Antenna ASICs . On-wafer measurements will be presented across multiple samples.

  • 11:20 Masum Hossain, University of Alberta (

    Affordable digital beamforming for 5G wireless

    The next generation wireless networks -- 5G -- promise wider bandwidth to enable wide range of applications including autonomous vehicle, virtual reality and internet of things. A key feature in these receivers is beamforming that compensates for pathloss and allows directional communication. Although digital beamforming is the holy grail in the antenna array technology, high resolution ADCs are not affordable in each receiver path at this speed. A more pragmatic approach is hybrid beamforming that combines RF and LO and digital where appropriate. First, cascaded PLL based LO beamforming is introduced that achieves lower phase noise and eliminate the high frequency clock distribution power. The cascaded PLL consumes 26.9-mW from a 1-V supply and achieves less than 100-fs integrated jitter with -116.2 dBc/Hz and -112.6 dBc/Hz phase noise at 1-MHz offset for the integer-N and the fractional-N modes, respectively. The fractional-N single-stage and cascaded PLLs achieve figure-of-merits (FoM) of -230.58 dB and -248.75 dB, respectively. The FoM of the proposed cascaded PLL outperforms that of the reported state-of-the-art mm-Wave synthesizers making it a suitable candidate for 5G transceivers. The digital beamforming takes advantage of the channel diversity by distributing the resolution according to channel SNR. In addition, it utilizes the correlated information between channels to perform energy efficient digitization of received signals. The collaborative ADC is designed with 8 SAR units each having 6-bit of resolution and 2-bit Flash to monitor SNR. With the help of a coarse 2-bit flash, the ADC can detect change in channel SNR, and accordingly reconfigure the four ADCs with variable resolution from 6-bit to 11-bit with less than 1 ns mode switching time. This collaborative ADC performance is compared with all 11- and all 9-bit. It reduces area and power by half and 41% respectively with only 10% degradation of overall SNDR.

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