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Emerging Technologies 2018 Session Listing

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Session P2: Plenary II

Start Time: 13:30, Friday, May 11
Room: Mt. Currie South
Chaired by Gord Harling, CMC Microsystems (

  • 13:30 Welcome Address: Gord Harling, CMC Microsystems (
  • 13:35 Gregory Snider, University of Notre Dame (

    Adiabatic reversible computation for ultra-low power

    Power dissipation is the most severe limiter of progress in computation today, and the heat generated can be enormous. For example, the waste heat generated by computers in data centers can provide all the heating necessary for their buildings, and excess heat is in some cases used to heat nearby towns. Data centers now consume a significant fraction of the electrical power produced, and this fraction is projected to continue increasing in the future. This dissipation is also an issue for small-scale computing, as evidenced by the heat produced by laptop computers, and the short battery life in mobile devices.


    The Landauer principle states that energy in computation must necessarily be dissipated only when information is destroyed. However, current CMOS technologies are very wasteful in energy because all information in the system is destroyed at each logic transition. Recent experiments have shown that the Landauer principle is correct, so that in theory there is no lower limit on energy dissipation in computational systems. Using adiabatic logic and logically-reversible architectures the destruction of information can be avoided and the energy used to encode information can be recovered and reused.


    This presentation will examine the challenges facing adiabatic reversible computation. Long dismissed because it requires reduced performance to save energy, adiabatic computing can offer compelling advantages. Today constraints of cooling, which sets a maximum power density, requires performance trade-offs such as multi-core, voltage scaling, and dark silicon. This presentation will explore the circumstances when the adiabatic reversible approach makes sense vs. the more established multi-core and dark-silicon methods. Devices and approaches needed for beyond CMOS implementations will also be examined.

  • 14:05 Juan Rey, Mentor Graphics (

    We are glad "you people" did not hear Moore’s Law is dead

  • 14:35 Mark Johnson, D-Wave Systems (

    Quantum annealing: a practical approach to quantum computing

    Last year D-Wave Systems announced general commercial availability and the first system order of its D-Wave 2000Q quantum computer. This system is D-Wave’s fourth generation quantum annealing processor, and is based on a superconducting integrated circuit chip implementing 2000 qubits. I will review quantum annealing (QA) as well as recent enhancements in the ability to control the QA algorithm. These include a new capability called "reverse annealing". I will discuss how these new features are being used to help develop potential applications.

  • 15:05 COFFEE BREAK (Mt. Curie Foyer)


  • 15:35 Purang Abolmaesumi, University of British Columbia (

    Advanced machine learning for ultrasound guided diagnosis and intervention

    In this talk, I present the development of advanced machine learning approaches for ultrasound-guided interventions and diagnosis. I will highlight three of the projects we are currently working on: 1) For the spine interventions, we have developed techniques that can automatically detect anatomical landmarks in ultrasound, and fuse ultrasound with a statistical model of the spine for guiding needle injections. 2) For prostate cancer diagnosis and treatment, we have demonstrated that automatic techniques can used for identifying cancer maps. Furthermore, we have developed techniques for automatic planning of prostate brachytherapy procedures. 3) For echocardiography, I will present the framework we have developed for automatic analysis of this data.

  • 16:05 Ricardo Reis, Universidade Federal do Rio Grande do Sul (

    Low-power issues in IoE

    The increasing number of devices connected to the internet is providing the concept of Internet of Things, that together with Internet of Health, Internet of People and Internet of Something is constructing the Internet of Everything (IoE). There is also an overlapping between IoT and CPS (Cyber Physical Systems) that have as components not only electronic ones, but also mechanical components, optical components, organic components, chemical components, etc. A keyword in IoT is optimization, mainly power optimization. Power optimization must be done in all levels of design abstraction, and at physical level is related to the number of transistors. Also, many systems are critical ones, like in Internet of Heath, where reliability is a major issue. Most of the circuits designed nowadays use much more transistors than it is needed. The increasing leakage power and routing issues are an important reason to optimize the number of transistors, as leakage power is related to the number of transistors. Also, the replacement of a set of basic gates by a complex gate reduces the number of connections to be implemented using metal layers as well the number of vias. The reduction of the number of connections to be implemented using metal layers helps to improve routing and also helps to improve reliability. To cope with this goal, it is needed to provide tools to automatically generate the layout of any transistor network.

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